EDN

Demonstrating ASIC IP performance and quality demands an FPGA-neutral design flow

Companies designing new system-on-chip (SoC) products are subject to ongoing market pressure to do more with less and achieve higher returns. The result is shrinking engineering teams, reduced design ...
Semiconductor Engineering

FPGA And System Designs Get To Market Faster Leveraging ASIC-Proven Analysis Tools

Digital systems need clocks. Today’s designs require more from clocking schemes than ever before, and it’s likely this trend will continue. Increasing power constraints have resulted in finer-grained ...
EDN

An FPGA primer for ASIC designers

With the advent of new technologies in IC design and complexity of the business models, chip designers may want to explore different choices available to them for implementation. ASICs have been the ...
Semiconductor Engineering

SpyGlass Application In An FPGA To ASIC Conversion Flow

Mapping from a field programmable gate array (FPGA) to an application specific IC (ASIC) is subject to some limitations. This white paper identifies some of the most common limitations in this mapping ...
DIGITIMES

Edge AI Demand Accelerates Shift from FPGA to ASIC for Vision Inference PGC's Design Service Turnkey Platform Helps Customers Move to ASIC and Short

As AI workloads move from cloud to edge, the volume of image and sensor data across industries is rising rapidly. Edge devices that previously relied on FPGAs and off-the-shelf modules are now running ...
Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM) Support

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.
Embedded

Moving from FPGA to ASIC for your AI chip? Here’s what you should know

Perhaps you are designing an embedded inference engine for edge computing. Or you are taking the next step in automotive vision processing. Or maybe you have an insight that can challenge Nvidia and ...
mccormick.northwestern.edu

COMP_ENG 355: ASIC and FPGA Design

This course will introduce students to practical design methodologies for developing applications for FPGAs and ASICs. You will learn the fundamentals for FPGA and ASIC design through software coding ...
Electronic Design

JESD204B Converters Simplify FPGA And ASIC Interfacing

JESD204B SERDES Tx and Rx facilitates connecting multiple high-speed, high-res data converters to FPGAs or ASICs. story describes how it does that with reduced pin-count and low, deterministic, ...
Business Wire

Aldec Cuts ASIC Design Prototype Bring-Up Time with HES-DVM’s Automatic Partitioning Tool and Faster HDL-to-FPGA Compilation Times

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has introduced automatic FPGA partitioning to ...
Ars Technica

Breaking into ASIC Design/Verification

I'm fast approaching the one year mark with my current employer since I graduated last year. Previously, I did three four month work terms with them and they were for the most part interesting. I took ...
Design News

Is Platypus from Zero ASIC the FPGA equivalent to RISC-V?

Before I tell you what I’m about to tell you, let’s first refresh our minds as to RISC-V processors. Why? Well, because even though what I’m about to tell you has nothing to do with RISC-V per se, in ...