EDN

HDL tool aids IC design flow

Version 6.0 of EASE design-entry environment for VHDL, Verilog, and mixed-language FPGAs and ASICs provides features for both advanced and novice HDL designers. HTML generation for any HDL design is ...
Design-Reuse

From Behavioral to RTL Design Flow in SystemC

This paper reports the scientific collaboration between LLR and PROSILOG. The aim of this collaboration was to show the possibility to quickly implement a system into a FPGA, using SystemC 4 as the ...
Design-Reuse

ACTEL and HDL Works Announce Optimization of Graphical HDL Design Entry Environment for Actel Design Flow

Companies Also Announce Addition of HDL Works to Actel's EDA Alliance Program CAMBERLEY, UK and EDE, Netherlands, July 26 -- Actel Corporation (Nasdaq: ACTL) and HDL Works today announced the ...
EDN

HDL: A Design Flow Runs Through It

The modern hardware design flow is beginning to resemble America's great rivers. At one time they ran wild and free, but now they are constrained by an endless series of irrigation projects, dams and ...
Electronic Design

Verilog-AMS Update Integrates With HDL Standard

The latest version of Accellera’s Verilog-Analog Mixed-Signal (AMS) standard, Verilog-AMS 2.3, unifies the standard’s previous version with IEEE Std. 1364-2005, the Verilog hardware description ...
Electronic Design

11 Myths About High-Level-Synthesis Techniques for Programming FPGAs

High-level synthesis to the rescue? You might be surprised at how hardware designers are getting new value from HLS when designing systems with FPGAs. The numbers of applications using FPGAs are on ...