EDN

An overview of SystemVerilog 3.1

SystemVerilog is an extensive set of enhancements to the IEEE 1364 Verilog-2001 standard. These enhancements provide powerful new capabilities for modeling hardware at the RTL and system level, along ...
EDN

How to implement DSP algorithms using the Xilinx Spartan-3E starter board

Editor's Note: This “How To” tutorial is an excerpt from a recently published book: Embedded Design Using Programmable Gate Arrays by Dennis Silage (ISBN-13: 978-1589094864). Dennis is a Professor in ...
Design-Reuse

Reusing Verilog IP Cores in SystemC Environment by V2SC

SystemC 2.1 supports all hardware concepts introduced by HDLs such as Verilog and VHDL. V2SC proposes a methodology for automatic conversion of Verilog 2001 constructs into SystemC 2.1 language. This ...