SAN FRANCISCO — A book about writing testbenches using SystemVerilog, written by Synopsys Inc.'s Janick Bergeron, has been published by Springer Science + Business Media, the company announced.

The electronics industry is constantly challenged by the ever-growing design and verification requirements for complex chips. With the IEEE-Std 1800-2005 System-Verilog standard, the industry has a ...

SystemVerilog marries a number of verification concepts, primarily in the areas of design, assertions, and testbench creation, that were previously embodied in separate and sometimes proprietary ...

Low power testbenches today have no visibility of the UPF objects and their states during a low power simulation. This has been one of the factors limiting the users from writing re-usable low power ...