EDN

Front-end analysis accelerates ASIC flow

The problem for Infrant Technologies, a young network storage IC company, was to figure out how to avoid the typical iterative design scenario. For our latest design, a 250-MHz network storage device ...
Electronic Design

ASIC Handoff Gets Physical As Front And Back Ends Converge

True or false: ASIC design follows a very straightforward path that begins with high-level architectural definition. It proceeds through RTL design and preliminary floorplanning. After synthesis, the ...
EDN

FPGA Front End Streamlines Transition to ASIC

Altera Corporation announced the HardCopy II family, its next-generation structured ASIC solution. HardCopy II devices are the industry's most compelling structured ASICs, featuring a unique FPGA ...
DIGITIMES

Edge AI Demand Accelerates Shift from FPGA to ASIC for Vision Inference PGC's Design Service Turnkey Platform Helps Customers Move to ASIC and Short

As AI workloads move from cloud to edge, the volume of image and sensor data across industries is rising rapidly. Edge devices that previously relied on FPGAs and off-the-shelf modules are now running ...
Semiconductor Engineering

Design of a Mixed-signal ASIC for the front-end electronics of ionisation chambers

New technical paper titled “An Ultra Low Current Measurement Mixed-Signal ASIC for Radiation Monitoring Using Ionisation Chambers,” by researchers at CERN. “Measurement of total ionizing dose in a ...